compliant to IEEE 1149.1
  – Due to limited pin count, JTAG is not supported on the 128-pin TQFP package. Features:
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*
*
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*
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having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1,.

Dual-Port RAM. The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. Registers on control, data, and address inputs provide minimal setup and hold times. The timing latitude provided by this a.

IDT70V3399

IDT70V3319

IDT70V3319S

IDT70V3379S

IDT70V3389S

IDT70V34

IDT70V34L

IDT70V34S

IDT70V35

IDT70V3569S

IDT70V3579S

IDT70V3589

IDT70V3589S